FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code.
Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.
FuseSoC makes it easier to
reuse existing cores
create compile-time or run-time configurations
run regression tests against multiple simulators
Port designs to new targets
let other projects use your code
set up continuous integration
FuseSoC is non-intrusive Most existing designs doesn’t need any changes to work with FuseSoC. Any FuseSoC-specific patches can be applied on the fly during implementation or simulation
FuseSoC is modular It can be used as an end-to-end flow, to create initial project files for an EDA tool or integrate with your custom workflow
FuseSoC is extendable Latest release support simulating with GHDL, Icarus Verilog, Isim, ModelSim, Verilator and Xsim. It also supports building FPGA images with Altera Quartus, project IceStorm, Xilinx ISE and Xilinx Vivado. Support for a new EDA tool requires ~100 new lines of code and new tools are added continuously
FuseSoC is standard-compliant Much effort has gone into leveraging existing standards such as IP-XACT and vendor-specific core formats where applicable.
FuseSoC is resourceful The standard core library currently consisting of over 100 cores including CPUs, peripheral controllers, interconnects, complete SoCs and utility libraries. Other core libraries exist as well and can be added to complement the standard library
FuseSoC is free software It puts however no restrictions on the cores and can be used to manage your company’s internal proprietary core collections as well as public open source projects
FuseSoC is battle-proven It has been used to successfully build or simulate projects such as Nyuzi, Pulpino, VScale, various OpenRISC SoCs, picorv32, osvvm and more.